Instruction-level parallelism in dataflow circuits
Exploiting control dependence to deliver data tokens earlier and enable more aggressive out-of-order execution in dynamically scheduled circuits generated from sequential programs.
Ayatallah (Aya) Elakhras
AI for Hardware Design · High-Level Synthesis · Computer Architecture
I am currently a Senior Researcher at Huawei Research Center in Zürich, working on next-generation Neural Processing Units (NPUs). My research interests span computer architecture, compilers, and hardware generation.
I completed my Ph.D. in Computer and Communication Sciences at EPFL in 2026, advised by Prof. Paolo Ienne (EPFL) and Prof. Lana Josipović (ETH Zürich). My doctoral research brought concepts from out-of-order superscalar processors into dynamically scheduled high-level synthesis (HLS) to exploit parallelism in dataflow circuits generated from sequential programs.
In 2023, I began a six-month research internship at AMD in Longmont, Colorado, under the supervision of Dr. Kristof Denolf, working on architecture-aware scheduling and design space exploration for mapping neural networks onto AMD AI Engines.
I earned my B.Sc. in Computer Engineering in 2020 from the American University in Cairo, graduating summa cum laude and started my Ph.D. in the same year.
News
November 2026
Joining Huawei Zürich Research Center as a Senior Researcher.
September 2026
Received my Ph.D. in Computer and Communication Sciences from EPFL.
August 2026
Successfully completed my public Ph.D. defense at EPFL.
June 2026
Passed my Ph.D. private oral examination at EPFL unconditionally.
March 2026
Best Paper Honorable Mention at ASPLOS’26!Our paper "Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits" received a Best Paper Honorable Mention.
February 2026
Best Paper Runner-up at FPGA’26!Presented our paper "Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS" at FPGA’26 in Seaside, California, where it received the Best Paper Runner-up recognition.
April 2025
Presented our paper "ElasticMiter: Formally Verified Dataflow Circuit Rewrites" at ASPLOS’25 in Rotterdam, the Netherlands.
September 2024
Google Ph.D. Fellowship!Awarded the Google Ph.D. Fellowship for exceptional doctoral research in Distributed Systems and Parallel Computing.
March 2024
Completed my research internship at AMD in Longmont, Colorado.
February 2024
Presented our paper "Survival of the Fastest" at FPGA’24 in Monterey, California.
October 2023
Started my research internship at AMD in Longmont, Colorado.
February 2023
Presented our paper "Straight to the Queue" at FPGA’23 in Monterey, California.
September 2022
Best Paper Award Nomination at FPL’22!Presented our paper "Unleashing Parallelism in Elastic Circuits with Faster Token Delivery" at FPL’22 in Belfast, Northern Ireland, where it was nominated for the Best Paper Award.
October 2020
EDIC Fellowship!Started my Ph.D. in Computer and Communication Sciences at EPFL and was awarded the EDIC Fellowship for incoming Ph.D. students with an exceptional academic record.
Research
Memory-level parallelism and access reordering
Designing lightweight interfaces to spatial load-store queues and custom memory-reordering circuits that exposememory-level parallelism without relying on conventional centralized load-store queues.
Fine-grained out-of-order execution
Introducing tagging mechanisms and circuit transformations that enable multiple independent execution contexts to progress simultaneously, bringing multithreading to dataflow circuits.
Related paperFPGA ’24 · Survival of the Fastest ↗
Formal verification of dataflow circuits
Collaborating with researchers at EPFL and ETH Zürich to establish the correctness of circuit transformations and out-of-order execution techniques through model checking andLean-based formal proofs.
Publications
Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits
Y. Herklotz, A. Elakhras, M. Camaioni, P. Ienne, L. Josipović, T. Bourgeat
Best Paper Honorable Mention
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS
R. Piryadi, A. Elakhras, M. Stojilović, P. Ienne
Best Paper Award Runner-up
ElasticMiter: Formally Verified Dataflow Circuit Rewrites
A. Elakhras*, J. Xu*, M. Erhart, P. Ienne, L. Josipović
* Equal contribution
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
A. Elakhras, A. Guerrieri, L. Josipović, P. Ienne
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits
A. Elakhras, R. Sawhney, A. Guerrieri, L. Josipović, P. Ienne
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery
A. Elakhras, A. Guerrieri, L. Josipović, P. Ienne
Best Paper Award Nominee
Honors & Awards
Best Paper Honorable Mention · ASPLOS’26
Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits.
Best Paper Award Runner-up · FPGA’26
Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS.
Google Ph.D. Fellowship
Awarded for exceptional Ph.D. research in Distributed Systems and Parallel Computing.
Best Paper Award Nominee · FPL’22
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery.
EDIC Fellowship · EPFL
Awarded by EPFL's School of Computer and Communication Sciences to incoming Ph.D. students with an exceptional academic record.
Summa Cum Laude · American University in Cairo
Graduated with honors with a B.Sc. in Computer Engineering.
Outstanding Academic Achievers’ Honors Assembly · American University in Cairo
Recognized for academic achievement.
Teaching & Mentorship
Teaching assistance · EPFL
Guided more than 200 bachelor's students through VHDL, Verilog, Nios II, and RISC-V assembly labs; co-designed midterm and final examinations.
Teaching assistance · American University in Cairo
Delivered tutorials introducing bachelor's students to MIPS assembly language.
Project supervision at EPFL
Yuan Qin
Improved the robustness of Fast Token Delivery by using Binary Decision Diagrams (BDDs) to represent complex control flow decisions.
Zeinab Pourgheisari
Extended the Gated Single Assignment MLIR library to support loops with multiple exits.
Giacomo Sansone
Studied where out-of-order execution is beneficial and implemented Fast Token Delivery in MLIR.
Dana Kossaybati
Automated tagged-component generation and implemented an MLIR transformation for out-of-order execution.
Anushka Allawadi
Implemented an MLIR pattern-matching rewriter for dataflow circuit optimization.
Teodor Cvijović
Implemented a control-dependence analysis pass in MLIR.
Ahmed Salem
Experimented with a VHDL library of tagged dataflow components.
Gianluca Radi
Implemented loop disordering and extended circuit interfaces to support multithreading.
Riya Sawhney
Researched a load–store queue interface to exploit dataflow parallelism.
Invited Talks
Custom Dataflow Circuits for Memory Access Reordering
Dynamically Scheduled High-Level Synthesis
Challenges in Reasoning about Dataflow Circuits
Design Space Exploration for AI Engines
Academic Service
EPFL doctoral admissions prefiltering committee
Evaluated doctoral applicants to EPFL's Ph.D. program.
Ph.D. application mentoring · EPFL
Supported prospective doctoral applicants by reviewing their application materials.
Primary reviewer · Journals
ACM Transactions on Design Automation of Electronic Systems (TODAES); IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
Secondary reviewer · Conferences
ACM/IEEE International Conference on Computer-Aided Design (ICCAD); ACM International Symposium on Field-Programmable Gate Arrays (FPGA); IEEE International Conference on Field-Programmable Logic and Applications (FPL); IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM).
Contact
The easiest way to reach me is by email.