Ayatallah Elakhras
I am a Ph.D. student at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland, working in the Processor Architecture Laboratory under the supervision of Paolo Ienne.
Between October 2023 and March 2024, I did an internship at AMD in the Research and Advanced Development team, under the supervision of Kristof Denolf.
I received a B.Sc. degree in Computer Engineering from the American University in Cairo (AUC), Egypt, in 2020 and started my Ph.D. in the same year.
My research interests include electronic design automation, computer architecture and compilers. My current research focuses on optimizing dataflow circuits generated for dynamically scheduled high-level synthesis.
Education
- Ph.D. in Computer and Communication Sciences, School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland (2020-Present)
- B.Sc. in Computer Engineering, School of Sciences and Engineering, The American University in Cairo (AUC), Egypt (2015-2020)
Fellowships and Awards
- Best Paper Award Nominee, 32nd International Conference on Field Programmable Logic and Applications (FPL) (2022)
- École Doctorale d’Informatique et de Communication (EDIC) Fellowship for new PhD students with an exceptional academic record, EPFL (2020)
- Outstanding Academic Achievers’ Honors Assembly, AUC (2018-2020)
Publications
- Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. In Proceedings of the 32nd ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, to appear, Monterey, CA, March 2024. [artifacts]
- Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. In Proceedings of the 31st ACM/SIGDA Intl. Symposium on Field Programmable Gate Arrays, pages 39-45, Monterey, CA, February 2023. [artifacts]
- Ayatallah Elakhras, Andrea Guerrieri, Lana Josipović, and Paolo Ienne. Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. In Proceedings of the 32nd International Conference on Field‐Programmable Logic and Applications, pages 253–61, Belfast, UK, August 2022.
Teaching
- Computer Architecture II (CS-209), School of Computer & Communication Sciences, EPFL (Spring 2021-2023)
- Computer Architecture I (CS-208), School of Computer & Communication Sciences, EPFL (Fall 2021-2022)
- Computer Organization and Assembly Language Programming (CS-231), Department of Computer Science & Engineering, AUC (Summer 2018)
Student Supervision
- Teodor Cvijovic (Summer@EPFL internship, 2023)
- Ahmed Essam Salem (Summer@EPFL internship, 2023)
- Gianluca Radi (M.Sc. semester project at EPFL, Spring 2023)
- Riya Sawhney (Summer@EPFL internship, 2022)
Professional Service
Student Member of ACM SIGARCH - WiCARCH - IEEE (2020-Present)
Secondary Reviewer
- ACM International Symposium on Field-Programmable Gate Arrays (FPGA)
- IEEE International Conference on Field‐Programmable Logic and Applications (FPL)
- IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
Primary Reviewer
- ACM Transactions on Design Automation of Electronic Systems (TODAES)
Industrial Experience
Contact